High speed design rules are followed. The four DDR2 databuses, DDR_D[0-7], DDR_D[8-15], DDR_D[16-23] and DDR_D[24-31] are length-matched using trombone routing or accordion routing to their respective clocks. The DDR_A bus is length-matched too. Non-DDR2 components are restricted from being inside the DDR2 keepout. Power supply pins are sensitive to noise and are carefully filtered.